This invention relates to integrated-circuit, nonvolatile memory arrays, including electrically-programmable, read-only memory (EPROM) arrays, and to circuitry for biasing the column lines of such arrays.
In particular, the invention relates to circuitry for maintaining the voltages of the column lines of such arrays at desired levels.
An EPROM array is one example of an integrated circuit that in which the circuit and method of this invention may be used. EPROM arrays include floating-gate memory cells arranged in rows and columns. The floating gate of a programmed memory cell is charged with electrons, and the electrons in turn render the source-drain path under the charged floating gate nonconductive when a chosen row-line select voltage is applied to the control gate. The nonconductive state is read as a "zero" bit. The floating gate of a non-programmed cell is neutrally charged such that the source-drain path under the non-programmed floating gate is conductive when the same chosen row-line select voltage is applied to the control gate. The conductive state is read as a "one" bit.
Each column and row of an EPROM array may contain thousands of cells. The sources of each cell in a column are connected to a virtual-ground line (source-column line). The drains of each cell in a column are connected to a separate bitline (drain-column line). The control gates of each cell in a row are connected to a wordline.
During cell programming, appropriate programming voltages are applied to the selected control-gate wordline and the selected drain-column line to create a high-current condition in the selected channel region, injecting channel-hot electrons and/or avalanche-breakdown electrons across the channel oxide to the floating gate.
Previous biasing circuits for virtual-ground memory arrays have biased the entire memory array, including biasing both drain-column lines and source-column lines (the latter also called virtual-ground lines). Biasing of that type is described in U.S. Pat. No. 4,722,075. The advantage of the biasing arrangement described in that patent is that all column lines are connected by a resistance to a common node, guaranteeing that all column lines (selected and deselected) have a discharging, or a charging, path such that none of the column lines are allowed to float. In the virtual-ground-array patent (U.S. Pat. No. 4,281,397), certain source-column lines are charged through a diode. That is, the deselected source-column lines nearest the memory cell being read are charged by a N-channel field-effect transistor configured as a diode. The diode-connected transistor provides no discharge path for the source-column lines. A discharge path is necessary for response to power supply voltage changes or for response to parasitic leakage paths to a higher-than-intended potential applied to an array terminal.
An inability to maintain source-column lines at the correct levels causes a difficult problem where a virtual-ground memory array has high operating speed requirements and/or has high capacitance source-column lines. When reading a conducting memory cell in such a virtual-ground memory array, if the memory cell sharing the same drain-column line and the same wordline has its source-column line at a higher voltage level than the drain-column line voltage level required for accurate sensing, the cell being read must also discharge that higher-voltage-level source-column line. The added discharge requirement slows the access time required to read the selected conducting memory cell.
The biasing arrangement disclosed in U.S. Pat. No. 4,722,075 is difficult to use with sense amplifiers having cascode circuits. When using cascode-type sense amplifiers, the bias set by the cascode devices on the drain-column lines must match the bias on the source-column lines. If the bias is not matched, the currents caused by the voltage differentials will degrade sensing capability. In addition, if the biasing arrangement disclosed in U.S. Pat. No. 4,722,075 is used in segmented architectures, the bias devices must be repeated in every segment.
There is a need for a circuit and method to control the biasing voltages on both the drain-column lines and the source-column lines of high-speed segmented virtual-ground memory arrays in a manner that overcomes the problems described above.